1. Field of the Invention
The present invention relates to a method of forming a metal-insulator-metal (MIM) capacitor on a semiconductor wafer, and more particularly, to a method of forming a metal-insulator-metal capacitor having low resistivity and being compatible with a dual damascene process metal runner.
2. Description of the Prior Art
A dual damascene process starts by making a trench and a via underneath the trench. A single metal layer is deposited to fill the trench and the via. Then, a chemical mechanical polish(CMP) process is performed to simultaneously form a metal runner and a plug with up and down piled structure. The dual damascene structure is used to connect different devices and runners, in various levels on a semiconductor wafer, and isolate them from other devices by forming inter-layer dielectrics around them.
The dual-damascene structure has the following advantages: 1) since a chemical mechanical polishing process finishes the process of making the dual damascene structure, the surface of the semiconductor wafer is extremely flat, which is very helpful in subsequent deposition and photo-lithography processes; 2) when preparing the inter-metal connection between the two metal layers, the openings of the metal line, and the via underneath the metal line, are formed during the same photolithography process, so the number of process steps can be reduced and the size of the device can be controlled more accurately; 3) the metal etching process step can be omitted, so the problem of volatile species not being easily expelled, as a result of metal etching, can be avoided. Therefore, the dual damascene structure is broadly applied in the manufacturing of integrated circuits. With the increasingly accurate and complex development of integrated circuits, it is a very important issue to lift the yield rate of the dual damascene structure.
In U.S. Pat. No. 6,037,664, Zhao et al. proposes a basic method of manufacturing dual damascene. Please refer to FIG. 1 to FIG. 9. FIG. 1 to FIG. 9 are schematic diagrams of a process for making a dual damascene structure 30 and an inter-metal connection 36 according to the prior art. As shown in FIG. 1, a semiconductor wafer 10 comprises a substrate 11 and an inter-layer dielectric (ILD) 12, the inter-layer dielectric 12 comprises a conductive region 13 and a conductive layer 14 disposed in the conductive region 13. The conductive region 13 is a portion of the lower level metal layer(not shown). Furthermore, the conductive region 13 can be a metal runner, a landing pad, a gate, a drain or a drain formed on the semiconductor wafer 10. A linear layer 15 is set between the conductive layer 14 and the inter-layer dielectric 12. The objective of the linear layer 15 is to isolate the conductive layer 14 and the inter-layer dielectric 12 in order to prevent metal atoms from diffusing into the inter-layer dielectric 12. The linear layer 15 is composed of titanium nitride(TiN), tantalum nitride(TaN) and silicon nitride(Si3N4), etc.
As shown in FIG. 2, a barrier layer 16, a first dielectric layer 18 and a first etch-stop layer 20 are sequentially deposited on the semiconductor wafer 10. The barrier layer 16 is a silicon nitride layer or a silicon dioxide layer and has a thickness of 300xcx9c1000 angstoms, depending on the composition of the conductive layer 14. The first dielectric layer 18 is a dielectric layer with a low dielectric constant and a thickness of 500xcx9c1000 angstroms. The first etch-stop layer 20 has a thickness of 300xcx9c1000 angstroms and its composition is necessarily different from that of the barrier layer 16. Usually a silicon dioxide layer is used.
As shown in FIG. 3, a first photolithography and etching process are performed by applying a first photoresist layer 19 and a first dry etching process. A first opening 21 is formed in the first etch-stop layer 20 above the conductive layer 14, then the first photoresist layer 19 is removed. The first opening 21 is used to form a via hole(not shown) in the subsequent process.
As shown in FIG. 4, a second dielectric layer 22 and a second etch-stop layer 24 on the semiconductor wafer 10 are sequentially deposited. Usually the composition of the second etch-stop layer 24 is the same as the composition of the first etch-stop layer 20. The composition of the second dielectric layer 22 is usually the same as that of the first dielectric layer 18.
As shown in FIG. 5, a second photolithography and etching process are then performed. By applying a second photoresist layer 23 and a second dry etching process, a second opening 25 is formed in the second etch-stop layer 24 above the conductive layer 14 and the first opening 21, then the second photoresist layer 23 is removed. The second opening 25 is used for forming the trench opening (not shown) in the subsequent process.
Then, as shown in FIG. 6, a low pressure plasma etching process, using oxygen as a reaction gas, is performed to remove the second dielectric layer 22 not protected by the second etch-stop layer 24, and to remove the first dielectric layer 18 not covered by the first etch-stop layer 20, down to the surface of the barrier layer 16. Because the compositions of the fist etch-stop layer 20 and the second etch-stop layer 24 are different from the composition of the barrier layer 16, a dual damascence structure 30 comprising a via opening 26 and a trench opening 28 can be formed by adjusting the selectivity. Also, since the barrier layer 16 is intact on the conductive layer 14, the conductive layer 14 can be protected.
Please refer to FIG. 7. A dry etching process, using methyl fluoride(CH3F) and oxygen as reaction gases, is then performed to remove the barrier layer 16 at the bottom of the via opening 26. When performing this process step, it is necessary to adjust the selectivity of solutions in order to avoid destroying the first etch-stop layer 20, the second etch-stop layer 24, the first dielectric layer 18 and the second dielectric layer 22.
As shown in FIG. 8, a metal layer 32 is deposited on the semiconductor wafer 10. The metal layer 32 can be a copper metal layer, an aluminum metal layer or other metal layer, and fills in the via opening 26 and the trench opening 28. Before forming the metal layer 32, a barrier layer 31 with a thickness of 100xcx9c1000 angstroms can be formed selectively, depending on the composition of the metal layer 32. The barrier layer 31 can be a titanium nitride layer or a tantalum nitride layer, and is used for isolating the metal layer 32 from the first dielectric layer 18 and the second dielectric layer 22.
As shown in FIG. 9, a chemical mechanical polishing process, using the second etch-stop layer 24 as a polish-stop layer, is then performed. The chemical mechanical polishing process removes the barrier layer 31 and the metal layer 32 above the second etch-stop layer 24, and makes the surface of the metal layer 32 and the barrier layer 31 flush with the surface of the second etch-stop layer 24. Finally, a third dielectric layer 34 is deposited. The composition of the third dielectric layer 34 is the same as that of the barrier layer 16. The third dielectric layer 34 covers the second etch-stop layer 24, the barrier layer 31, and the metal layer 32 processed by the chemical mechanical polishing treatment, to complete the metal runner 36 structure.
In U.S. Pat. No. 6,117,747, Shao et al. proposes a method for forming a metal-oxide-metal(MOM) capacitor by applying the dual damascence process. Although this method can avoid direct contact between a capacitor dielectric layer and a silicon substrate, which incurs the existence of interface trapped charges and results in stretch-out of the C-V curve under high frequency, the process steps are not simplified enough because the bottom metal layer, the oxide layer and the top metal layer still need to be made separately.
Although the method for forming the dual damascence structure 30 according to the prior art has the advantages mentioned above, the process can only produce the metal runner 36. Also the process steps of the method proposed by Shao are very complicated. Therefore, it is important to develop a dual damascence process that is capable of processing other devices, such as a metal-insulator-metal (MIM) capacitor, and is capable of reducing the process steps. Additionally, given the structure of MIM capacitors, when the conductive layer 14 and the metal layer 32 in the dual damascence process are both copper, these two layers can be applied as the top electrode and the bottom electrode, respectively. In this case, the top and the bottom electrodes of the MIM capacitor will have very ideal resistivity values, because the resistivity of copper is very low.
According to the prior art method for forming the dual damascence structure 30, when the conductive layer 14 is composed of a non-copper metal, usually a silicon dioxide layer together with a metal layer are used as the barrier layer 16. In the subsequent etching process of via opening 26, the silicon dioxide layer is applied as the etch-stop layer. However, when the conductive layer is a copper metal layer, usually a silicon nitride layer is used as the barrier layer 16 and the etch-stop layer in subsequent via opening etching processes. In the manufacturing process of the MIM capacitor compatible with the metal runner dual damascence process, these characteristics can be applied. So, there is no need to do an extra deposition for an isolation layer as the dielectric layer of the MIM, as the silicon nitride layer can be applied as the dielectric layer of the MIM directly. At the same time, due to the dielectric constant (∈) for silicon nitride layer being higher than that of the silicon dioxide layer, more charges can be stored under the same applied voltage. Making a MIM capacitor using silicon nitride as dielectric layer will also occupy less area on chip than the MIM capacitor with a silicon dioxide dielectric layer, so chip size also shrinks. Therefore, it is very important to develop a MIM capacitor with low resistivity electrodes and the above mentioned advantages, compatible to the copper runner dual damascence manufacturing process.
It is therefore a primary objective of the present invention to provide a method of forming a metal-insulator-metal (MIM) capacitor on a semiconductor wafer, the MIM capacitor being compatible with a copper runner dual damascence process.
The method according to the present invention provides a method of simultaneously forming a dual damascence runner and a metal-insulator-metal capacitor on a semiconductor wafer. The semiconductor wafer comprises a first dielectric layer, at least one first conductive layer, and at least one bottom electrode disposed in the first dielectric layer. A barrier layer covers the surface of the first conductive layer and the bottom electrode of the MIM capacitor. First, a second dielectric layer, a stop layer and a third dielectric layer on the barrier layer are sequentially formed. The second dielectric layer, the stop layer and the third dielectric layer together form a sandwiched structure. Thereafter, a first photoresist layer is formed on the surface of the third dielectric layer. The third dielectric layer not covered by the first photoresist layer is anisotropically etched down to the stop layer, forming a trench and an opening in the third dielectric layer above the first conductive layer and the bottom electrode of the MIM capacitor, respectively. The first photoresist layer is removed completely, a second photoresist layer is formed on the surface of the semiconductor wafer. The stop layer and the second dielectric layer are etched at a bottom of the opening down to the barrier layer, forming a top electrode opening of the MIM capacitor in the third dielectric layer, the stop layer and the second dielectric layer. The second photoresist layer is removed and a third photoresist layer is formed on the surface of the semiconductor wafer. Then, the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening, down to the surface of the conductive layer, forming a contact hole in the stop layer, the second dielectric layer and the barrier layer. The third photoresist layer is then removed. Finally, a metal barrier layer and a copper metal layer are formed. The copper metal layer fills in the contact hole, the trench and the opening of the top electrode of the MIM capacitor. Then, a chemical mechanical polishing process is performed, and an isolation layer is deposited, to complete the manufacturing of the copper runner and the MIM capacitor, respectively.
It is an advantage of the present invention that the method of forming the dual damascence structure will simultaneously form the MIM capacitor and the copper runner. Not only is the number of process steps reduced, but the resistivity value of the top and bottom electrodes are also reduced, and the chip size is shrunk.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.